Tritoncore-I has three main components. The high-level FPGA core that brings the lower level components together, the general routing table (GRT) which routes lookup tables together, and the lookup tables(LUTs) themselves, which are each individually capable of recreating any 4 input, 1-output combinational logic block.
This is the high-level module, described in FPGACore.scala
If you want to skip the descriptions and start coding, look at the links to the right.
This is a tutorial on setting up the tools this project, including all of its components.
It will walk you though compiling the core and the other project components, then taking some verilog code down to bitstream and testing on the Tritoncore-I emulator.
This is the second part of the tutorial, after setting up the FPGA emulator and the toolchain.
It will walk you through taking verilog code, using yosys to convert it to a netlist, and using the bitstream generator to convert it to a bitstream that the FPGA uses as input