Included with your download from github is the exported TritoncoreI verilog, plus a testbench example which loads a bitstream into the FPGA core, and runs a few inputs through it.
All necessary files are included in the verilog folder, located under the top of the TritoncoreI directory.
For convenience, and.bits is included with the files. However, you should try renaming the and.bits file and replacing it with your own to make sure that you successfully ran through the rest of the toolchain.
Install Vivado:
If you are on Ubuntu, the fastest way to get running is to go follow this tutorial. Tested on Ubuntu 16.04 with Oracle-Java-8 SDK and JRE.
you can also use Modelsim to run the testbench, as well. However, modelsim free edition ran at about 1/4th the speed for me, taking 4 hours to complete the test bench.
Run the testbench in vivado:
$ /opt/Xilinix/Vivado/....../bin/vivado
Create a new project, and select TritoncoreI/verilog as the location. Import all verilog files, and add and.bits as a simulation source.
Make sure you include and.bits as a simulation source!!!
Set test_core as the top-level module if necessary. At the bottom of your screen, you will see a tcl console. type
> run all
into the console to start the simulation.
You're done! You now have the entire toolchain running. Give yourself a pat on the back.
On the next pages, there is a tutorial on how the final Verilog for the FPGA core was actually generated. If you plan to help develp the on the Tritoncore project, you will need this information. (STILL TODO!!)