Within the FPGA there are two main components.
The General Routing Table, which connects lookup tables together, and the lookup tables themselves.
The routing table allows the output of any lookup table to be routed to the input of any other lookup table. However, each of the four inputs to the lookup tables can only accept input from one quarter of all the lookup table outputs. This is still much more routing than any production FPGA would use.
There are 240 LUTs and 16 inputs because this gives us a nice round 256 inputs to the GRT. there are 960 outputs from the GRT because each of the 240 LUTs have 4 inputs.
There are 16 LUTs which are hard-wired to the output. These are LUTs 0-15.
The FPGA is programmed in the following order:
1. Lookup tables from 0 to 239
2. Routing for lookup tables, in order from 0 to 239