Tritoncore-I has a very small goal: an FPGA which has a full software stack for programming it. The tritoncore-I only has 16 inputs, 16 outputs, and 240 LUTs. There is nothing else to it. The routing table allows routing of any LUT output to the input of any other LUT. This is slow, bulky, and unnecessary, but it simplifies the software side. We are using yosys to generate the netlist, and our own software for generating the bitstream. At this point, we officially have every component working.
We are not plainning on synthesizing the Tritoncore-I, though future iterations may get to the pont where they can be synthesized. We are currently planning Tritoncore-II, which will be the Tritoncore-I's bigger brother, with integrated memory blocks, somewhere around 1,000+ LUTs, and more efficiently designed routing.
Enough talk though, lets check out the Tritoncore-I!